1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a cascode circuit used for the purpose of decreasing output voltage fluctuations in response to power supply voltage fluctuations.
2. Description of the Related Art
In order to improve the power supply rejection ratio of an analog circuit, a method of adding a cascode circuit is conventionally widely used. Take as an example a reference voltage circuit, which is used to obtain stable output voltage in response to power supply voltage fluctuations and temperature changes. Conventionally, a circuit as illustrated in FIG. 2 of Semiconductor Device for Reference Voltage (Japanese Examined Patent Publication No. Hei 7-74976) is used. FIG. 2 illustrates an equivalent circuit. In the conventional reference voltage circuit, a source terminal of a depletion type MOS transistor 1 and a drain terminal of an enhancement type MOS transistor 2 are connected in series between a power supply voltage supply terminal 101 and a ground potential 100, and respective nodes and their gate terminals are commonly connected. The node is used as a reference voltage output terminal 102 (the electrical circuit such as shown in FIG. 2 will hereinafter be referred to as “a ED type reference voltage circuit 200”). Insofar as the respective transistors operate in a saturation state, even if the voltage of the power supply voltage supply terminal 101 fluctuates, the reference voltage output terminal 102 is not affected by the voltage fluctuations.
However, actually, the voltage of the reference voltage output terminal 102 fluctuates under the influence of channel length modulation effect of the depletion type MOS transistor 1. Accordingly, it is difficult to construct a reference voltage circuit having a high power supply rejection ratio. In order to suppress the channel length modulation effect and to suppress the fluctuations of the power supply voltage within a short period from affecting the reference voltage, a circuit illustrated in FIG. 3 is also used.
In the reference voltage circuit as illustrated in FIG. 3, a depletion type MOS transistor 3 is provided between the reference voltage circuit and a power supply voltage supply terminal 101. In the depletion type MOS transistor 3, a backgate terminal is used as a ground potential, and a bias voltages supply means 201 is connected to the gate terminal.
The depletion type MOS transistor 3 operates as a so-called cascode circuit, and operates so that voltage supplied to the ED type reference voltage circuit 200 becomes constant against the voltage fluctuations of the power supply voltage supply terminal 101. FIG. 1 of Reference Voltage Circuit and Electronic Device (Japanese Patent Application Laid-open No. 2003-295957) illustrates an actual structure of the bias voltage supply means 201. FIG. 4 illustrates a circuit equivalent to FIG. 1 of Japanese Patent Application Laid-open No. 2003-295957.
The circuit is a reference voltage circuit having two channel reference voltage outputs. Paying attention to the ED type reference voltage circuit 200, it can be thought that the depletion type MOS transistor 3, which operates as the cascode circuit is connected to the ED type reference voltage circuit 200, and the depletion type MOS transistor 3 is connected to the bias voltage supply means 201 including a depletion type MOS transistor 6, an enhancement type MOS transistor 7, and a depletion type MOS transistor 8. Similarly, it can be estimated that the depletion type MOS transistor 8 is connected to a bias voltage supply means including the depletion type MOS transistor 1, the enhancement type MOS transistor 2, and the depletion type MOS transistor 3.
In recent years, because mobile devices are widely available and for other reasons, the needs for the realization of a lower power consumption circuit, which can operate for a longer time with a battery of the same capacitance, is increasing. Along with the above circumstances, a reference voltage circuit having a comparable or superior performance to that of that conventional one, and still can operate at lower voltage is advantageous.
In the circuit as illustrated in FIG. 4, when backgate terminals of all the transistors are at the ground potential, consider the lowest operating voltage where no deterioration in the power supply rejection ratio is observed. To this end, all the transistors forming a circuit are required to perform the saturated operation.
In this case, gate-source voltages of the depletion type MOS transistors 3 and 8 each become zero when the characteristics of the two ED type reference voltage circuits are equal, and the characteristics of the depletion type transistors 3 and 8 each operate as a cascode circuit are equal, respectively. Therefore, the lowest operating voltage VDD(min) is expressed as the following equation:VDD(min)=Vref+|VT2(VSB2=Vref)|+|VT3(VSB3=Vref+|VT2(VSB2=Vref)|)|,  (Equation 1)where Vref is an output voltage of the reference voltage output terminal 102, VT2(VSB2=Vref) is a threshold voltage of the enhancement type MOS transistor 2 when the source-backgate voltage is Vref, and VT3(VSB3=Vref+|VT2(VSB2=Vref)|) is the threshold voltage of the MOS transistor 3 when the source-backgate voltage is Vref+|VT2(VSB2=Vref)|.
When the power supply voltage becomes lower than VDD(min) expressed in Equation 1, the depletion type MOS transistors 3 and 8, which operate as a cascode circuit operate in an unsaturation state, and thus, the output resistance becomes small and the power supply rejection ratio is considerably deteriorated.